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7-4

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

7.2 Types of Addresses

An address of a ladder logic instruction can indicate any of the following

items:

S A bit whose signal state is to be checked

S A bit to which the signal state of the logic string is assigned

S A bit to which the result of logic operation (RLO) is assigned

S A bit that is to be set or reset

S A number that indicates a counter that is to be incremented or

decremented

S A number that indicates a timer to be used

S An edge memory bit that stores the previous result of logic operation

(RLO)

S An edge memory bit that stores the previous signal state of another

address

S A byte, word, or double word that contains a value with which the ladder

element or box is to work.

S The number of a data block (DB or DI) that is to be opened or created

S The number of a function (FC), system function (SFC), function block

(FB), or system function block (SFB) that is to be called

S A label that is to be jumped to

Variables as addresses include an address identifier and a location within the

memory area indicated by the address identifier. An address identifier can be

one of the following two basic types:

S An address identifier that indicates both of the following:

– The memory area in which an instruction finds a value (data object)

on which to perform an operation (for example, I for the

process-image input area of memory, see Table 6-5)

– The size of the value (data object) on which the instruction is to

perform its operation (for example, B for byte, W for word, and D for

double word, see Table 6-5)

S An address identifier that indicates a memory area but no size of a data

object in that area (for example, an identifier that indicates the area T for

timer, C for counter, or DB or DI for data block, plus the number of that

timer, counter, or data block, see Table 6-5.

Possible

Addresses

Address Identifiers

Addressing

1 2 ... 91 92 93 94 95 96 97 98 99 100 101 ... 317 318

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