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8-6

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

8.5 Midline Output

The Midline Output instruction is an intermediate assigning element that

stores the RLO. This intermediate assigning element saves the bit logic

combination of the last open branch until the assigning element is reached. In

a series with other contacts, the Midline Output functions as a normal

contact.

The Midline Output instruction is affected by the Master Control Relay

(MCR). For more information on how the MCR functions, see Section 20.5.

Certain restrictions apply to the placement of a Midline Output. For example,

a Midline Output element can never be located at the end of a network or at

the end of an open branch. See also Section 6.1.

You can create a negated output by using the Invert Power Flow instruction.

Table 8-4 Midline Output Element and Parameter

LAD Element Parameter Data Type Memory Area Description

<address> BOOL I, Q, M, D, L

The address indicates the bit to which

the RLO is assigned.

For the Midline Output instruction, you can only use an address in the L memory area if you declare it in VAR_TEMP.

You cannot use the L memory area for an absolute address with this instruction.

The following Midline Outputs have the following RLOs:

M 0.0 has the RLO of

M 1.1 has the RLO of

M 2.2 has the RLO of the complete bit logic combination.

I 1.0

Status Word Bits

I 1.1

BR CC 1 CC 0 OV OS OR STA RLO FC

Write – – – – – 0 x –

M 0.0

I 1.2 I 1.3

NOT

M 1.1

NOT

M 2.2

Q 4.0

I 1.0 I 1.1

I 1.2 I 1.3

NOT

I 1.0 I 1.1 M 0.0

Figure 8-4 Midline Output

Description

Bit Logic Instructions

1 2 ... 99 100 101 102 103 104 105 106 107 108 109 ... 317 318

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