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8-22

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

8.21 Address Negative Edge Detection

The Address Negative Edge Detection instruction compares the signal state

of <address1> with the signal state from the previous signal state check

stored in <address2>. If there is a change from 1 to 0, output Q is 1.

Otherwise it is 0.

Certain restrictions apply to the placement of the Address Negative Edge

Detection box (see Section 6.1).

Table 8-20 Address Negative Edge Detection Box and Parameters

LAD Box Parameter Data Type Memory Area Description

<address1> BOOL I, Q, M, D, L

Signal to be checked for a

negative edge transition

NEG

M_BIT

M_BIT BOOL Q, M, D

The address M_BIT indicates

the edge memory bit that stores

the previous signal state of NEG.

Use the process-image input (I)

memory area for the M_BIT only

if no input module already

occupies this address.

Q BOOL I, Q, M, D, L One-shot output

Status Word Bits

BR CC 1 CC 0 OV OS OR STA RLO FC

Write x – – – – x 1 x 1

I 0.0 I 0.2I 0.1

I 0.3

NEG

M_BIT

M 0.0

Q 4.0

I 0.4

Output Q 4.0 is 1 if the following

conditions exist:

S The signal state is 1 at inputs I 0.0

And I 0.1 And I 0.2

S And there is a negative edge

at input I 0.3

S And the signal state is 1 at

input I 0.4

Figure 8-20 Address Negative Edge Detection

Description

Bit Logic Instructions

1 2 ... 115 116 117 118 119 120 121 122 123 124 125 ... 317 318

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