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B-9

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

A signal check of timer T 1 produces the result of logic operation (RLO, see

Section 6.2) shown in Figure B-6.

250 ms

Figure B-6 RLO for Negated T 1 Contact in the Clock Pulse Timer Example

As soon as the time runs out, the timer is restarted. Because of this, the signal

check made by ––| / |–– T 1 produces a signal state of 1 only briefly.

Figure B-7 shows what the negated (inverted) RLO bit looks like.

250 ms

Figure B-7 Negated RLO Bit of Timer T 1 in the Clock Pulse Timer Example

Every 250 ms the RLO bit is 0. The jump is ignored and the contents of

memory word MW100 is incremented by 1.

Table B-5 lists the frequencies that you can achieve from the individual bits

of memory bytes MB101 and MB100. Network 5 in the ladder logic diagram

shown in Figure B-5 illustrates how the MOVE instruction allows you to see

the different clock frequencies on outputs Q12.0 through Q13.7.

Table B-5 Frequencies for Clock Pulse Timer Example

Bits of

MB101/MB100

Frequency in Hz Duration

M 101.0 2.0 0.5 s (250 ms on/250 ms off)

M 101.1 1.0 1 s (0.5 s on/0.5 s off)

M 101.2 0.5 2 s (1 s on/1 s off

M 101.3 0.25 4 s (2 s on/2 s off)

M 101.4 0.125 8 s (4 s on/4 s off)

M 101.5 0.0625 16 s (8 s on/8 s off)

M 101.6 0.03125 32 s (16 s on/16 s off)

M 101.7 0.015625 64 s (32 s on/32 s off)

M 100.0 0.0078125 128 s (64 s on/64 s off)

M 100.1 0.0039062 256 s (128 s on/128 s off)

M 100.2 0.0019531 512 s (256 s on/256 s off)

Achieving a

Specific

Frequency

Programming Examples

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