
36 Texas Instruments Communication Driver Manual
PLC ID
The format for the PLC ID for the model 315 will include both the PLC ID and a memory register
used for the two Bit Write registers. The format will be the PLC ID followed by the memory address.
XX-IOYYY or XX-YYY or XX
Where
XX PLC ID in range 1-90
- PLC ID/memory address separator
IO Optional memory type
YYY Optional Starting IO byte memory address in range 0-340.
Note: In the PLC ID field, IO will default to a byte address.
The memory address must be on an 8-bit boundary. If an IO memory address is not entered, the Bit
Write register will default to IO340. The following ladder logic rungs are an example of setting and
clearing bits that may be added to a model 315 program for the purpose of setting and clearing
individual bits.
Example 1:
With a bit write to IO054, the Operator Station will write 54 octal (44 decimal). Rung 1 tests
for bit pattern 0010 1100 in byte IO340 and set IO054.
The Operator Station will also write 254 octal (172 decimal) to byte IO340. Rung 2 tests for
bit pattern 1010 1100 in byte IO340 and resets IO054.
Example 2:
With a bit write to IO213, the Operator Station will write 13 octal (11 decimal). Rung 3 tests
for bit pattern 0000 1011 in byte IO350 and sets IO213.
The Operator Station will also write 213 octal (139 decimal) to byte IO350. Rung 4 tests for
bit pattern 1000 1011 in byte IO350 and re-sets IO213.
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