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Semiconductor Group 3 - 16

Memory Organization

A hardware protection is done by an unsymetric latch at XMAP0-bit. A unintentional disabling of

XRAM could be dangerous since indeterminate values could be read from external bus. To avoid

this the XMAP-bit is forced to ’1’ only by reset. Additional during reset an internal capacitor is loaded.

So the reset state is a disabled XRAM. Because of the load time of the capacitor XMAP0-bit once

written to ’0’ (that is, discharging capacitor) cannot be set to ’1’ again by software. On the other hand

any distortion (software hang up, noise,...) is not able to load this capacitor, too. That is, the stable

status is XRAM enabled. The only way to disable XRAM after it was enabled is a reset.

The clear instruction for the XMAP0-bit should be integrated in the program initialization routine

before XRAM is used. In extremely noisy systems the user may have redundant clear instructions.

The control bit XMAP1 is relevant only if the XRAM is accessed. In this case the external RD

and

signals at P3.6 and P3.7 are not activated during the access, if XMAP1 is cleared. For debug

purposes it might be useful to have these signals available. This is performed if XMAP1 is set.

3.4.3 Behaviour of Port0 and Port2

The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register

SYSCON and on the state of pin EA

. The table 3-3 lists the various operating conditions. It shows

the following characteristics:

a) Use of P0 and P2 pins during the MOVX access.

Bus: The pins work as external address/data bus. If (internal) XRAM is accessed,

the data read from the XRAM can not be seen on the bus.

I/0: The pins work as Input/Output lines under control of their latch.

b) Activation of the RD

and WR pin during the access.

c) Use of internal or external XDATA memory.

The shaded areas describe the standard operation as each 80C51 device without on-chip XRAM

behaves.

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