
INTRODUCTION
1-3
1.2 Technical Information
The E1 interface of ETx is fully comply with ITU-T recommendation G.703 and
G.704. This module supports configurable CRC-4 option to enhance
transmission integrity. E bit (Remote End Block Error bit) defined in ITU-T
Rec. G.704 is also supported, helping carrier with an easier solution to monitor
the E1 aggregate link. Physical interfaces of E1 links on ETx 901xU are
unbalanced, 75-ohm resistance, terminated by female BNC connectors. ETx
901xB with balanced, 120-ohm resistance, terminated by mini terminal-blocks.
ETx 901xE with unbalanced, 75-ohm resistance, terminated by Siemens 1.6/5.6
connectors.
The ETx module is Hot Swappable, which minimizes system downtime by no
power down insertion/replacement. Whenever there’s a need to re-initialize
hardware, reset switch can be reached on faceplate.
The MARS 9000 system is implemented with an in-built DACS (Digital Access
Cross-connect System). It supports comprehensive and flexible cross-connect
functionalities such as:
Ø Interchange time-slot between E1 ports on the same ETx module.
Ø Interchange time-slot between E1 ports and TDM buses.
Ø Interchange time-slot between TDM buses on the same system.
Ø Cross-connect between E1 ports and TDM buses (per 32 time-slot).
It reduces the cost for buying more ports on external DACS and utilizes E1
trunks at highest efficiency by managing local cross-connect traffic.
Due to the design of this in-built DACS function, no traffic can pass directly
from one tributary to another. All the data from tributaries must be forwarded to
TDM bus in order to be directed to the destination.
The timing mode of ETx can be one of three options: Recover from E1
1
,
Generate internal clock and External clock. If more than one ETx modules are
coexisting on one MARS9000 system, only one of them can be in Master
2
mode
and the others should be in Slave mode. An ETx in Master mode will be the
timing source of entire MARS 9000 system, including TDM bus and all other
tributaries. The other ETx in Slave mode will follow the clock from TDM bus.
The timing clock feeding into EXT CLOCK connector must be G.703 unframed
all ‘1’ signal and the acceptable accuracy is ±50 PPM (±5.0 x 10
-5
).
*Note
1 Refer to Clk Source Sel in section 2.5.3 SYSTEM MANAGE for
timing clock options
2 Refer to Clk Source Mode in section 2.5.3 SYSTEM MANAGE
for the necessary steps to setup an ETx in Master and Slave mode.
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